Typically the rim portion 19 will be thicker than diffused layer 15 but thinner then the sum of the thicknesses of layers 11 and 15. 2, 3, and 5 are straightforward and have been alluded to earlier.

4, there is shown a prior art chip 40 that includes two p-n junctions 14A and 14B in a symmetrical arrangement to form either a p-n-p or n-p-n structure depending on the choice of resistivity of the starting material. All rights reserved. Nos. 3, there is shown a chip 30 in which central depressions 31 and 32 have been formed on opposite surfaces 30A and 30B, respectively, of the chip 30 before formation of diffused layers 13 and 15. the substrate is etched back to leave the transistor isolated from surrounding material. With respect to the last reference, note particularly pages 298+ for a discussion of the etching and photo-resist aspects of the known technology. Thus, any current that flows is due to the very weak process of carrier generation inside the depletion region due to When the reverse bias becomes very large, reaching the breakdown voltage, the generation process in the depletion region accelerates leading to an This equation does not model the non-ideal behavior such as excess reverse leakage or breakdown phenomena. The semiconductive device of claim 3 further comprising a passivating layer extending over the side walls of the mesa portion.5. The semiconductive device of claim 5 further characterized in that a diffused layer extends over the back surface, and separate electrode connections are provided on said front and back surfaces.7. Photo courtesy of Red Mesa School District, Teec Nos Pos, Arizona. 1 with electrode 16A on layer 13A, electrode 16B on layer 13B, and dual dielectric layers 18 with one covering a portion of bulk portion 11 and a portion of the surface 40A and the other covering a portion of bulk portion 11 and a portion of the surface 40B.Referring now to FIG. The silicon material would typically be provided in wafer form and be doped to be either of the "N" or "P" type.

1 as the result of the formation of a depressed or thinned central region 12B in the wafer 11 before the formation of the rectifying junction 14 so that the contour of the junction 14 follows the contour of the now-depressed top surface 20A of the chip 20. 7 shows the wafer 50 after the thinning of a central portion by anisotropic wet etching of the top surface 50A to leave a central depression 51 with sloped side walls 51A. 2.FIG. As a result, the tops of the mesas get higher and higher above the surrounding areas in each cycle. This tends to result in a thicknesses for the rim region 19 that makes for breakage and lowered yields in manufacture.Referring now to FIG. 1). 257/417, 257/623, 257/E21.219, 257/E21.231, 257/E21.251, 257/E21.285, 438/53, 438/911, 438/977 This permits leaving more of the original thickness of the wafer in the area of the moat. The operation of the exemplary pressure sensor 10 is described in the above-referenced application Ser. 9, by dicing the wafer 50 at the region of the moat 55, either before or after the formation of a passivating layer 57. 2016-July, 7520815, Institute of Electrical and Electronics Engineers Inc., pp. In essence a transistor consists of an area of either p type of n type semiconductor sandwiched between regions of oppositely doped silicon. Geography. A bottom surface of the chip typically includes a diffused surface layer 15 (a contact layer) that is of the same conductivity type but of lower resistivity than the bulk portion 11. Other features and advantages will be apparent from the specification and claims and from the accompanying drawings, which illustrate an exemplary embodiment of the invention. Symmetric central depressions can be formed in the same etching step simply by leaving central portions of with surface 30A and 30B unmasked during the anisotropic etching step.

4,467,394 of Grantham & Swindal, the inventors hereof, issued Aug. 21, 1984. Advantageously, the starting wafer has been cut so that its top and bottom surfaces lie on <100> crystal planes of the wafer to provide sloped walls to the depressions.Moreover, in accordance with other embodiments, the bottom surface of the chip is also etched to have a surface topology that is essentially a mirror image of the topology of the top surface of the chip.Viewed from one perspective the present invention is a semiconductive device which comprises a semiconductive chip that includes a bulk portion of a first conductivity type and a mesa portion on a front surface of the bulk portion. A p-n junction created on silicon with electrodes is a diode. 2. using a silicon substrate and in the oxidation process forming a layer of silicon dioxide on the exterior surface of the silicon substrate. Each cycle includes a photolithographic operation to protect the previously grown oxide in the mesa area(s) from etching. However, if so desired, a single substrate with a single mesa could be individually made. With particular reference to FIGS. During each cycle less oxide is grown (or conversely silicon consumed) on the mesas than in the preceding cycle, while equivalent amounts of oxide are grown on non-mesa areas in each cycle. The top structure uses a mesa to avoid a sharp curvature of the p +-region next to the adjoining n-layer. 1, there is shown a prior art silicon diode formed on a silicon chip 10. 2 with electrical contact 16A over layer 13A and electrical contact 16B over layer 15, and separate dielectric layers 18 over portions of the bulk portion 11 and partly over the surfaces 40A and 40B.